Critical area computation for missing material defects in VLSI circuits

Abstract

We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in very large scale integration yield prediction. Missing material defects cause open circuits and are classified into breaks and via blocks. Our approach is based on the L/sub /spl infin// medial axis of polygons and the weighted L/sub /spl infin// Voronoi diagram of segments. We also introduce the min-max Voronoi diagram of rectangles, a combinatorial structure of independent interest. The critical area problem for breaks and via blocks is reduced to variations of weighted L/sub /spl infin// Voronoi diagram of segments. Plane sweep algorithms to compute the appropriate Voronoi diagrams for each case are presented. As a result, the critical area for breaks and via blocks on a single layer can be computed accurately in one pass of the layout. The time complexity is O(n log n) in the case of breaks and O((n+K)log n) in the case of via blocks, where n is the size of the input and K is upper-bounded by the number of interacting vias (in practice K is small). The critical area computation assumes square defects and reflects all possible defect sizes following the D(r)=r/sub 0//sup 2//r/sup 3/ defect size distribution. The method is presented for rectilinear layouts.