Abstract
CPU packages continue to undergo significant changes to keep pace with demands of high performance silicon to meet market needs. In the last decades or so, increasingly CPU performance and frequency levels couples with lower product cost have been driving new package technologies. This paper illustrates an approach in CPU package design optimization for performance improvement and package cost reduction through effective capacitor usage and package layer count reduction. This involves the new proposed package stack-up designed to lower packaging cost and as well as mixed type capacitor usage in package power delivery.
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