Co-verification design flow for HDL languages: A complete development methodology

Abstract

During the design of complex systems implemented in field programmable gate arrays (FPGA), an estimate of about 60% of the designer's time is spent for testing, including nonregression simulations and on-board tests [1]. In this perspective, it is key to guarantee the perfect match of hardware description language (HDL) coding with the algorithm. This has to be achieved without compromise on code quality. To satisfy these requirements, an innovative design methodology has been set-up. We propose a straightforward approach to model the algorithm, in order to ease the implementation task and to reduce turnaround from HDL design back to system modeling. This methodology also enables automation of all steps from the simulation model down to the in-situ test on board. This paper will depict the tools and languages used to co-verify the algorithm with the HDL implementation, down to the delivery. This flow does not use any High Level Synthesis tools, but is rather focused on HDL design productivity improvement. This methodology benefits from open source tools used in software development that we have adapted to the HDL.