Coverage modeling for verification of floating point arithmetic units

Abstract

Coverage modeling is one of the fundamental tasks of the verification flow in systems development. The resulting model is commonly used to evaluate the progress and quality of the verification process, it also provides a useful abstraction for the generation of test vector patterns. This work presents an heuristic approach for coverage model definition based on the concepts of equivalence classes and boundary-value analysis to address the verification of floating point arithmetic units. As a case study, a coverage model was designed to verify the ADD operation of a floating point module for the binary16 number format defined in the IEEE 754-2008 standard, and a SystemVerilog testbench was implemented to perform the verification process. The effectiveness of the heuristic and the quality of the resulting model are analysed by measuring the coverage obtained in the execution of a third party test suite, and by generating a set of test vectors from the model and stimulating a design under verification (DUV) to detect bugs for design review.