Abstract
The coupled thermo-mechanical field analysis of three-dimensional (3D) stacked integrated circuits (ICs) is evaluated by an efficient and accurate simulation strategy that combines equivalent homogenization modeling methodology and sub-modeling technique. The thermal field is first investigated using the proposed approach, and based on which the structural field is also examined through the calculation of warpage. The utilization of sub-modeling method reveals the local temperature and warpage distributions, which is lost or ignored by the conventional homogenization method. To validate the proposed method, the simulation results of a five-layer stacked integrated circuits are compared against true 3D results of the detailed model, where the maximum deviation for temperature and warpage is as low as 1.62% and 4.89%, respectively, which are greatly improved compared to 8.23% and 7.83% using traditional homogenization method. In addition, the total computation time is reduced by 76.7% in contrast to true 3D finite element analysis (FEA) simulation. Furthermore, the impacts of through-silicon-via (TSV) geometries, underfill and μ -bump parameters on the temperature and warpage distributions are also studied to guide the design of 3D ICs with high performance and reliability.
Highlights
Three-dimensional (3D) integration has been attracting considerable attention because it vertically stacks multifunction chips by a mass of through-silicon-vias (TSVs) to establish electrical interconnect among stacked chips, thereby overcoming the obstacle encountered during the shrinking of traditional planar integration and realizing complex 3D integrated circuits (3D ICs) with small form factor, high density, and excellent performance [1]–[5]
This paper has presented a modeling and simulation strategy for implementing the coupled thermal and structural analyses of 3D ICs with TSVs
By combining the equivalent homogenization method with the advanced sub-modeling technique, the proposed method is able to reveal the detailed temperature and warpage information as true 3D finite element analysis (FEA) analysis based on the detailed model does, but the total computation time is reduced by 76.7%, thereby overcoming the inherent weakness of conventional equivalent method
Summary
Three-dimensional (3D) integration has been attracting considerable attention because it vertically stacks multifunction chips by a mass of through-silicon-vias (TSVs) to establish electrical interconnect among stacked chips, thereby overcoming the obstacle encountered during the shrinking of traditional planar integration and realizing complex 3D integrated circuits (3D ICs) with small form factor, high density, and excellent performance [1]–[5]. After the chip containing TSVs or the interlayer with μ-bump is homogenized with the equivalent thermal and structural properties, its detailed information inside the equivalent block or black box is discarded, thereby resulting in a globally correct but locally inaccurate evaluation for the thermo-mechanical performance of 3D ICs. it is highly desired to explore a method, which can accelerate the simulation without losing the detailed local information. The equivalent model of 3D ICs is constructed utilizing the homogenized material above for following thermal and structural analyses, after which the global temperature and warpage distributions are obtained.
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