Counter Tree: A Scalable Counter Architecture for Per-Flow Traffic Measurement

Abstract

Per-flow traffic measurement, which is to count the number of packets for each active flow during a certain measurement period, has many applications in usage accounting, traffic engineering, service provision and anomaly detection. In order to maintain the high throughput of routers or switchers, the per-flow traffic measurement module should use high-bandwidth SRAM that allows fast memory accesses. Due to the limited SRAM space, exact counting, which requires to keep a counter for each flow, does not scale to large networks consisting of numerous flows. Some recent work takes a different path to accurately estimate the flow sizes using counter architectures that can fit into tight SRAM. However, existing counter architectures have some limitations, either still requiring considerable SRAM space, or having a very small estimation range. In this paper, we design a scalable counter architecture Counter Tree which leverages a two-dimensional counter sharing scheme to achieve far better memory efficiency and significantly extend estimation range. The extensive experiments with real network trace demonstrate that our counter architecture can produce accurate estimates for flows of all sizes even under a very tight memory space, e.g., 2 bits per flow.