Cost-sensitive FPGA implementation of SAR range-doppler algorithm

Abstract

Synthetic aperture radars (SAR) are widely recognized in the remote sensing community for their imaging capabilities. A SAR system, either on an aircraft or on a satellite, allows the acquisition of high-resolution images of a comprehensive area over the flight path. Being an active sensor, it does not have as many restrictions to visibility as optical sensors and can operate even at night. Moreover, considering the wavelength used, images can be collected through clouds or even through treetops. SAR data processing, like other remote sensing processing, is computationally intensive, and platforms like Graphics Processing Units (GPUs) [1], [2], [3] and Field Programmable Gate Arrays (FPGAs) [4] are options to increase the computational performance. GPUs implementations are software oriented, thereby, they are simpler to implement, but due to their ample computational resources, their power consumption is high. A FPGA platform allows a customized architecture and its power consumption is lower. However, FPGA implementations require digital design expertise due to its hardware-oriented conception [5] which impact the development time.