Cost Modeling for SOC Modules Testing

Abstract

The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore's law. There is big challenge of testing this comp lex VLSI circuit, in which whole system is integrated into a single chip called System on Ch ip (SOC). Cost of testing the SOC is also increasing with comp lexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered fro m the prev ious work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLA B, which can be used as a cost estimat ion tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimat ion tools for test planning.