Correlation of surface morphology and chemical state of Si surfaces to electrical properties

Abstract

We have studied the structure of silicon surfaces and interfaces from an atomic to a macroscopic scale by low energy electron diffraction (LEED), scanning tunneling microscopy (STM), and angle-resolved light scattering (ARLS). Subsurface damage was determined on silicon wafers using modulated optical reflectance (MOR) measurements. The chemical state of silicon wafers prepared by different cleaning procedures was characterized by X-ray photoelectron (XPS) and high resolution electron energy loss spectroscopy (HREELS) measurements. It is shown that chemo-mechanical polishing and subsequent epitaxy produce very smooth surfaces. The existence of atomic steps is proved by electron and photon diffraction. During semiconductor device processing steps (see fig. 1), however, the smoothness of the polished surface deteriorates in most cases again. It is demonstrated that thermal oxidation of silicon leads to pronounced roughness at the SiSiO 2 interface. This roughening depends on the virgin silicon surface morphology and its chemical state due to different cleaning procedures, on ulk properties, on storage time prior to oxidation, and on the parameter of oxidation. The extent of the roughness increase may be used to monitor the process performance. Besides the influence of the interfacial structure on mobility, interface states, and fixed oxide charges the impact of interface degradation on the dielectric breakdown behaviour will be demonstrated. By plasma treatments and oxidation on purpose roughened Si wafers the determination of a threshold in terms of interface degradation is made possible. Beyond this limit the dielectric breakdown field will be affected severely.