Correlation Between the Strain on the Printed Circuit Board and the Stress in Chips for the Failure Prediction of Passive Components

Abstract

Due to the demand for miniaturization of microelectronic devices, the density of packaging has become higher and higher. Also, the sizes of components have become smaller and smaller. In addition to advanced active components such as chip scale packages (CSPs) and flip chips (FCs), mini sized passive components such as chip capacitors and resistors are also important elements for high density packaging. It is quite common to see dozens up to hundreds of passive components on printed circuit boards (PCBs). Both active and passive components contribute to the function (and also malfunction) of electronic systems. However, the reliability issues of passive components are often overlooked because they are relatively small in size and cheap in cost. In view of the fact that “small components could lead to big problems”, the present study is conducted to evaluate the threat to passive components assembled on PCBs under a specific type of mechanical loading. Because of the nature of mass production, microelectronic devices are always manufactured in a batch mode. It is quite often that several PCBs are linked together during the surface mount assembly process. Even if the PCB is a stand-alone unit, extra peripheral frames or tie bars are needed for tooling and fixture. After the board level assembly, a depaneling process is usually required to singulate individual PCBs or to remove the tooling frames for the system level assembly. Some depaneling processes may be automated with precision control. However, it is not unusual for operators in the factory to perform manual depaneling. During this process, the PCB is subjected to mechanical bending and the curvature of the bent PCB may be big enough to damage small passive components. The present study is intended to establish a model for the failure prediction of passive components under depaneling load condition. Computational stress analysis is performed with a 3D finite element model. The emphasis is placed on finding the correlation between the bending strain on the PCB (which is an index of the local curvature of the bent PCB) and the bending stress in the passive components (which is the reason to crack capacitors/resistors). It is observed that such a relationship can be established. With this model, the cracking of passive components may be predicted under the depaneling load condition. The understanding of this potential threat can be turned into a design rule to avoid mounting passive components in the “high risk” area on the PCB. As a result, the objective of “design for reliability” (DFR) can be achieved. The details of the aforementioned model and the results of stress analysis will be presented in this paper.