Coresidual alias-locked loops

Abstract

A coresidual alias-locked loop (C-ALL) introduces a technique to reduce spurs in the voltage-controlled oscillator (VCO) output of an alias-locked loop (ALL). The output of an ALL subsampler provides a digital aliased frequency, that when in lock, is a recurring sequence of 1's and 0's at an average frequency of the reference clock. The lack of alignment of this bitstream to the reference clock can produce spurs on the VCO output. The C-ALL solves the problem by predicting the expected pattern of 1's and 0's and provides this signal to the phase detector to compare with the subsampler. The expected pattern is generated in the digital domain as the reference signal to the PFD, therefore a C-ALL implements a coresidual function. Functional simulation in Spectre has verified that the proposed design can not only achieve lock but also reduce output spur by 34.82 dBc.