Coreless substrate with asymmetric design to improve package warpage

Abstract

Coreless substrates have been used in more and more advanced package designs for their benefits in electrical performance and reduction in thickness. However, coreless substrate causes severe package warpage due to the lack of a rigid and low CTE core. In this paper, both experimental measured warpage data and model simulation data are presented and illustrate that asymmetric designs in substrate thickness direction are capable of improving package warpage when compared to the traditional symmetric design. A few asymmetric design options are proposed, including Cu layer thickness asymmetric design, dielectric layer thickness asymmetric design and dielectric material property asymmetric design. These design options are then studied in depth by simulation to understand their mechanism and quantify their effectiveness for warpage improvement. From the results, it is found that the dielectric material property asymmetric design is the most effective option to improve package warpage, especially when using a lower CTE dielectric in the bottom layers of the substrate and a high CTE dielectric in top layers. Cu layer thickness asymmetric design is another effective way for warpage reduction. The bottom Cu layers should be thinner than the top Cu layers. It is also found that the dielectric layer thickness asymmetric design is only effective for high layer count substrate. It is not effective for low layer count substrate. In this approach, the bottom dielectric layers should be thicker than the top dielectric layers. Furthermore, the results show the asymmetric substrate designs are usually more effective for warpage improvement at high temperature than at room temperature. They are also more effective for a high layer count substrate than a low layer count substrate.