Abstract
This paper discusses the architectural aspects for the implementation of blind carrier frequency offset (CFO) estimation in orthogonal frequency division multiplexing (OFDM) systems using coordinate rotational digital computer (CORDIC). Multiplexed-stream architecture (MSA) for the considered CFO estimation algorithm has been designed and evaluated for field programmable gate array (FPGA) implementation using Xilinx system generator (XSG) tool. The proposed architecture is a resource-efficient implementation where a single fast Fourier transform (FFT) core can be shared between the parallel-streams. The effect of finite hardware precision on the CFO estimation accuracy is accessed in terms of mean square error (MSE). The simulation results demostrated that the proposed architecture consumes at least 25% less resources compared with the parallel-stream implementation.
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