Abstract
Through silicon vias (TSVs) play a critical role in today’s microelectronic technology as they enable fabrication of three-dimensional integrated circuits. Traditionally, copper has been used to fill TSVs. However, copper is prone to electro-migration and as the size of TSVs become smaller, copper resistance increases significantly, thereby reducing its potential for TSV material at nanoscales. A proposed hybrid structure is presented here in which Carbon Nanotube (CNT) bundles are grown vertically inside TSVs and encased with copper. The CNT bundles assists with increasing the strength of the hybrid structure and is likely to enhance the reliability of the package. Thermo-mechanical stress analysis and reliability evaluations is conducted to determine the effect of CNT bundles on stress distribution in the package and their impact on reliability of other critical components such as solder bumps that are used to join the silicon layers. The finite element analysis shows that addition of CNT material to the structure, even in small volume ratios tend to redistribute the stress and refocus it to inside the CNT material rather than interfaces. Interface stresses in low strength material typically cause delamination and failure in the package. Redistribution of stress is likely to enhance the reliability of the TSVs. Additional reliability analysis of the solder joints, shows that CNT additions enhances the number of cycles to failure four times. It is hypothesized that addition of CNTs decreases the local CTE mismatch between the silicon layers and assists in reducing the stress in solder bumps. This hypothesis is proven using finite element simulations.
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