Abstract

This work describes an improvement in the layout of coplanar electrodes for electrical impedance spectroscopy. We have developed, fabricated, and tested an improved electrode layout, which improves the sensitivity of an impedance flow cytometry chip. The improved chip was experimentally tested and compared to a chip with a conventional electrode layout. The improved chip was able to discriminate 0.5 μm beads from 1 μm as opposed to the conventional chip. Furthermore, finite element modeling was used to simulate the improvements in electrical field density and uniformity between the electrodes of the new electrode layout. Good agreement was observed between the model and the obtained experimental results.

Highlights

  • Electrical impedance spectroscopy (EIS) is a relatively new technique, which has evolved from the Coulter Counter principle [1]

  • The technique has been used in multiple applications within the field of flow cytometry [5], including applications that involve biological samples, such as white blood cells in different states [5] or bacteria detection and characterization [4,6,7]

  • The work described in this paper presents an optimized electrode layout for a microfluidic electrical impedance flow cytometer, which increases the sensitivity of the device

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Summary

Introduction

Electrical impedance spectroscopy (EIS) is a relatively new technique, which has evolved from the Coulter Counter principle [1]. Improvements in the sensitivity of multi-frequency EIS systems, without increasing the hydraulic resistance of the channel, have great potential, as it will allow simultaneous detection and better characterization of a wider size range of particles. The work described in this paper presents an optimized electrode layout for a microfluidic electrical impedance flow cytometer, which increases the sensitivity of the device. The advantage of this electrode layout compared to previous ones reported is that this layout achieves higher sensitivity without introducing complicated sample focusing by, e.g., dielectrophoresis/electrophoresis (DEP/EP). The FEM was used to simulate the electrical field in the improved and conventional layout system and the simulations were compared with the obtained data to explain the results

Chip Design and Co-Planar Electrode Layout
Finite Element Modeling
Chip Fabrication and Measurement Setup
Measurements
Electrode Dimension Optimization with FEM
Chip Characterization
Conclusions
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