Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications

Abstract

Augmented reality (AR) SoCs exhibit sequential memory access patterns, enabling domain-specific optimization of SRAM for low power. This work co-designs SRAM internal operation sequences, low-power write-assist techniques, and SRAM-SoC interfaces. A 7nm 1MB sequential SRAM demonstrates 52% lower read energy and 58% lower write energy. These sequential access operation modes further allow 18% higher operating frequency and less than 1.6% cycle count overhead based on workload benchmarking. This custom memory is integrated in an electromyography (EMG) input prototype wristband for AR glasses to enable low-energy hand gesture detection. The results demonstrate integration of a novel SRAM design and are a step towards meeting thermal and battery constraints of AR products.