Cooling Computer Chips with Cascaded and Non-cascaded Thermoelectric Devices

Abstract

Thermoelectric devices are currently being used in cooling and generating electricity applications. This study mainly focuses on using thermoelectric devices for both applications towards cooling down computer chips; especially, that the very large scale integration technology has reached high advancement where more than 100 million transistors can be fabricated in 1 mm2. Reducing the non-uniformity of the chip temperature is important so as to decrease the induced thermal stress in this chip and consequently reduce its failure rate. To simultaneously reduce both the non-uniformity of the temperature distribution in the chip and the power requirements for the cooling system, thermoelectric generators can be installed on the cooler chip areas to harvest electrical power from the chip wasted heat. Thereafter, the chip hotspot areas are cooled down using thermoelectric coolers that are powered by the harvested electrical power from the thermoelectric generators in order to maintain the temperatures of these hotspots to be less than or equal a certain temperature threshold. Because no additional electrical power requirement is needed to cool down the hotspots, this cooling technique is called in this paper as “sustainable self-cooling framework for cooling chip hotspots”. However, the question is that can the harvested electrical power by the thermoelectric generators be enough to power the thermoelectric coolers for different computer chips at a given operating condition? As such, one of the objectives of this paper is to develop a three-dimensional numerical and optimization model to predict the thermal and electrical performance of cascaded and non-cascaded thermoelectric generators and cascaded and non-cascaded thermoelectric coolers for cooling chip applications. Then, validate the developed model against experimental data. The results showed that the predictions of the developed model were in good agreement with the experimental to within ± 4%. After gaining confidence in the developed model, it was used for a given chip operating condition to conduct a case study for a sustainable self-cooling framework in order to answer the raised question above. The results showed that the self-cooling framework can successfully cool down the hotspot at an acceptable temperature with not only no need for additional electrical power requirements but also for reducing the non-uniformity in the chip temperature distribution.