CooLBIST: An Effective Approach of Test Power Reduction for LBIST

Abstract

Low power design is becoming the mainstream in VLSI. However, since most of the technologies minimizing power consumption have only focused on normal mode operation, test mode operation is often posing the high power consumption because of the high switching activity during scan shift operation. On the other hand, test data volume has become big issue as the size of digital designs continues to grow. Logic built-in self-test (LBIST) is well known as one of the technologies to reduce test data volume. In general, LBIST uses pseudorandom pattern generator (PRPG) with high switching activity. Therefore LBIST makes high power consumption during scan shift operation. As the results, it increases test time (costs) because test engineer has to slow down shift speed to solve power issue. Now, we propose new technique called CooLBIST that controls switching activity during scan shift operation of LBIST. Application result shows that new activity control technique succeeds in reducing the switching activity during scan shift operation without a decline in fault coverage.