Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

Abstract

Latches have the advantages of timing-borrowing, smaller cell area, lower input capacitance, and lower power compared to flip-flops (FFs). This article presents a CAD flow that converts any arbitrarily complex single-clock-domain FF-based RTL design into an efficient 3-phase latch-based design. The flow includes a novel 3-phase aware retiming algorithm for power and area optimization. Post place-and-route results demonstrate that our new 3-phase designs achieve 23.5% and 23.9% average power reductions compared to more traditional FF and master–slave-based alternatives across a board range of benchmarks with no degradation in performance and on average less area.