Controlling metastable native point-defect populations in Cu(In,Ga)Se2 and Cu2ZnSnSe4 materials and solar cells through voltage-bias annealing

Abstract

This contribution describes the influence of low-temperature annealing with and without applied voltage bias on thin-film Cu2ZnSnSe4 (CZTSe), Cu(In,Ga)Se2 (CIGS), and CdS material properties and solar cell performance. To quantify the effects of cation disorder on CZTSe device performance, completed devices were annealed under open-circuit conditions at various temperatures from 110 °C to 215 °C and subsequently quenched. Measurements on these devices document systematic, reversible changes in solar-cell performance consistent with a reduction in CZTSe band tails at lower annealing temperatures. CIGS and CZTSe solar cells were also annealed at various temperatures (200 °C for CIGS and 110 °C–215 °C for CZTSe) and subsequently quenched with continuously applied voltage bias to explore the effects of non-equilibrium annealing conditions. For both absorbers, large reversible changes in device characteristics correlated with the magnitude and sign of the applied voltage bias were observed. For CZTSe devices, the voltage-bias annealing (VBA) produced reversible changes in open-circuit voltage (VOC) from 289 meV to 446 meV. For CIGS solar cells, even larger changes were observed in device performance: photovoltaic (PV) conversion efficiency of the CIGS device varied from below 3% to above 15%, with corresponding changes in CIGS hole density of about three orders of magnitude. Findings from these VBA experiments are interpreted in terms of changes to the metastable point-defect populations that control key properties in the absorber layers, and in the CdS buffer layer. Computational device modeling was performed to assess the impacts of cation disorder on the CZTSe VOC deficit, and to elucidate the effects of VBA treatments on metastable point defect populations in CZTSe, CIGS, and CdS. Results indicate that band tails impose important limitations on CZTSe device performance. Device modeling results also indicate that non-equilibrium processing conditions including the effects of voltage bias can dramatically alter point-defect-mediated opto-electronic properties of semiconductors. Implications for optimization of PV materials and connections to long-term stability of PV devices are discussed.