Abstract

An application of the macro dataflow computer architecture in controlling industrial processes is described in this paper. The DFCL — a relatively low level data-flow language and a complier, which transforms programs written in this language into program graphs with different levels of granularity are presented first. A suitable macro data-flow industrial controller (IC) model architecture, which was theoretically studied and simulated is described next. The inputs in the simulation are: an fined grained dataflow graph, a number of processors, a communication delay times and execution times for simple nodes. The outputs are: a waiting tokens profile, a parallelism profile, a waiting nodes profile in queue, the program graph with optimal grain size and scheduling strategy for nodes of the program graph. The above research work was done simultaneously with the development of a real, but conventional IC so that many useful comparisons have been done. This has shown the enormous increase in performances of the data-flow IC and pointed out that it is a viable candidate for future industrial controllers.

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