Abstract

Combined input and output queued (CIOQ) architectures with a moderate fabric speedupS > 1 have come to play a major role in the design of high performance switches. In this paper we study CIOQ switches in two settings. The first is a setting of a single CIOQ switch with Priority Queuing (PQ) buffers, which provide better Quality of Service (QoS) guarantees by decreasing the delay experienced by mission-critical and real-time traffic. The second is a setting of a Multistage Interconnection Network (MIN), where each Switching Element (SE) is a CIOQ switch. In the first setting, we consider the case of traffic with packets having variable values. The goal of the switch policy is to maximize the total value of packets sent out of the switch. We present a switch policy that is 6-competitive for any speedup. In the second setting, we study a MIN architecture in which each internal buffer is further divided into virtual buffers, one per each MIN output port reachable from that buffer. We consider the case of traffic with unit value packets, and the goal of the policy managing the MIN is to maximize the total number of packets sent out of the MIN. We give a local memoryless switch policy that uses back pressure and achieves a competitive ratio of (4h + 1), where h is the number of stages of the MIN. The proposed policy is simple and can be efficiently implemented at high speeds. We also demonstrate a lower bound of h/2 on the competitive ratio of any local work-conserving deterministic memoryless switch policy. We further show that without back pressure, no online local work-conserving deterministic switch policy can break the competitive ratio of [Formula: see text], where N is the size of the MIN and k is the size of an SE.

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