Controller synthesis using data-driven clocks

Abstract

The traditional methods of design for asynchronous sequential machines involve a careful study of the flow table to identify and deal with the critical races and hazards. This often leads to additional state variables and extra hardware as well as complicating the design method. The necessity for such special considerations means that asynchronous designs cannot take advantage of the CAD tools developed for synchronous machines. The aim of this paper is to present a self-clocked methodology for the implementation of asynchronous sequential circuits which is comparable in simplicity and reliability with synchronous methods, while retaining the advantages of the asynchronous approach. The overall strategy has been to generate data dependent clocks locally to toggle individual state variables, and to self-synchronize the change of state variables thereby eliminating the problems of races and hazards. The proposed method is illustrated by its application to the design of a VMEbus requester.