Abstract
Polishing-induced nanotexture (i.e., unintended variations in surface figure of varying dimension) has been observed in optical fabrication for decades. It is also commonly observed in the Chemo-Mechanical Polishing (CMP) of integrated circuit wafers. Historically, CMP-induced nanotexture has not been a significant problem until the implementation of front end of the line (FEOL) structures required to overcome scaling effects on device performance. By the transition to 10nm scale devices, film thickness variation due to nanotexture is expected to become a significant process issue that must be overcome. In this paper we review the impact of the effect in device processing, outline several major sources of nanotexture, and routes to mitigate their effect.
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