Abstract
A new concept in control of cascaded H-Bridge multi-level inverters is proposed in this paper. According to this concept, switching angles are considered to be independent from the fundamental voltage. A polynomial term is presented to show the relation between switching angles and DC voltages. Based on this concept, Total Harmonic Distortion (THD) calculations are updated and proved to be independent from the fundamental voltage. Thus, once calculated for minimum THD, the switching pattern can be used for any required level of output voltage. To examine the effectiveness of the proposed method, it is applied in control of an eleven level inverter. The simulation results are demonstrated and verified through experiments with a setup controlled by Xilinx SPARTAN3 family FPGA (XC3S400-PQG208).
Highlights
Multi-level inverters have come a long way since the first time proposed for High Voltage DC applications
In [7], fault ride through (FRT) capability of the generators are analyzed in a hybrid transmission line including an overhead line and an underground cable and a novel data-mining based method is proposed for fault location which is very fast and accurate
The optimization results are found through Genetic Algorithm optimization method, and effectiveness of the proposed method is verified through an experimental set up and using a Xilinx SPARTAN3 FPGA
Summary
Multi-level inverters have come a long way since the first time proposed for High Voltage DC applications. Modularity, and module level maximum power point tracking, cascaded H-bridge multilevel inverter topology has become an attractive configuration over the past years. This topology is seen as the most suitable topology for the integration of the renewable energies to power system. Several well-known switching techniques have been introduced over the past two decades to control the output voltage of the inverter while minimizing THD of the output waveform These techniques include sinusoidal pulse width modulation (SPWM) [12], carrier pulse width modulation [13], space vector pulse width modulation (SVPWM) [14], and selected harmonic elimination pulse width modulation (SHEPWM) [15]. The optimization results are found through Genetic Algorithm optimization method, and effectiveness of the proposed method is verified through an experimental set up and using a Xilinx SPARTAN3 FPGA
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