Control Flow Checking Optimization Based on Regular Patterns Analysis

Abstract

With the continuous sub-micron process scaling, reliability of integrated circuits has quickly become a first-order design concern. In modern computing systems, transient errors are increasingly likely to corrupt the computation by altering the control flow or sequencing of instructions, leading to catastrophic failures. Prior work on control flow checking provides good coverage but at a high cost. In this paper, by exploring regular control flow patterns found in most applications, we propose the optimization schemes for software signature control flow checking that could reduce the error detection overheads. Specifically, we leverage the fact that most applications have: (1) simple fan-in / fan-out control flow patterns, and (2) most of control flows can be predicted during the compilation stage through static branch prediction heuristics. By exploiting these opportunities, we propose two techniques to reduce the number of inserted codes at common paths and simplify control flow checking of irregular patterns with minimal overheads. Experimental results on a variety of applications demonstrate that our approaches could reduce checking overhead by almost 2.5x on average while leading to similar fault coverage compared to traditional control flow checking.