Abstract
When applications exhibit more complex control flow behaviors, wide single-instruction multiple-data (SIMD) architecture is inefficient, which mainly due to two aspects, vector condition branch and nested loop. To solve this problem, this paper proposes two independent ideas: the data-aware thread-level parallelism (DATLP) and hardware-supported software pipeline scheduling policy (HSSP). They share the same hardware which is the instruction buffer queue (IBQ), to improve the efficiency by increasing Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP). Compared with the traditional SIMD-architecture, the proposed control-enhanced power SIMD, will get an average performance improvement by 84% for a wide variety of media and 4G wireless communication applications, while the area overhead only increases by 2.97%.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
