Abstract
In this paper, we propose a novel delta-sigma modulator (DSM) that reduces the effects of clock jitter and excess loop delay by using a vector filter in the feedback path. The vector filter divides the input signal into a high-frequency part and a low-frequency part. The low-pass signal is placed in the path to the first-stage digital-to-analog converter for reducing the effects of the clock jitter, and the high-pass signal is placed in the feedback path to the last integrator in order to compensate for the excess loop delay. The DSM using the vector filter in the feedback path (DSM-VF) is verified using MATLAB/Simulink. Further, a clock jitter (0.1 %) in DSM-VF leads to an improvement in the signal-to-noise-ratio (SNR) to 22.5 dB as compared to the SNR of a conventional CTDSM. Moreover, the SNR deterioration caused by the excess loop delay is improved.
Highlights
In the recent years, the use of complementary metal-oxide semiconductor (CMOS) miniaturization technology has led to improvements in the digital circuit used in electrical equipment
In this paper, we propose a novel delta-sigma modulator (DSM) that reduces the effects of clock jitter and excess loop delay by using a vector filter in the feedback path
The lowpass signal is placed in the path to the first-stage digitalto-analog converter for reducing the effects of the clock jitter, and the high-pass signal is placed in the feedback path to the last integrator in order to compensate for the excess loop delay
Summary
The use of complementary metal-oxide semiconductor (CMOS) miniaturization technology has led to improvements in the digital circuit used in electrical equipment. These improvements have led to a considerable increase in the demand for high-speed, highprecision analog-to-digital converters (ADCs) in order to leverage the advanced digital circuit technology. 4, a design method of the proposed system is explained, and Sect. The effect of the current mismatch caused by the variation of the transistor performance is explained The latter half of the section verifies the influence of variations and mismatches of multi-bit DAC followed by the conclusion in Sect.
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