Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile

Abstract

The effects of an amorphous Si gate on various electrical fluctuations were evaluated for aggressively scaled CMOS transistors. After developing an advanced amorphous Si gate stack that effectively suppressed gate depletion, we measured intra-wafer fluctuations in gate capacitance and threshold voltage (Vth). The amorphous Si gate decreased intra-wafer fluctuations, intrinsic fluctuations of the scaled transistors, asymmetric fluctuation of the threshold voltage, and fluctuation in threshold voltage mismatch between neighboring transistors in the SRAM. Based on these results, we estimated a yield of the scaled SRAM for 45 nm technology node.