Abstract
Contest (cone-oriented test pattern generator), an ATPG (automatic test pattern generation) tool for very large combinational digital circuits, is presented. Contest is based on four major ideas. Cone-oriented circuit partitioning reduces the circuit complexity and increases the number of dominators. The propagation graph is a dynamic data structure that keeps track of all paths from the fault location to a primary output. The multiple backtrace procedure reduces contradictory node assignments by examination of fanout nodes and dynamic implications. The pattern parallel fault dropping technique is based on Hamming distance variations of generated test patterns. Experimental results for benchmark circuits containing up to 40000 nodes illustrate the superiority of the ATPG system. For these circuits a 100% fault coverage for all detectable stuck-at faults and a 100% redundancy identification are achieved. >
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