Abstract

Network-on-Chip (NoC)-based multiprocessor system-on-chips (MPSoCs) are becoming the de-facto computing platform for computationally intensive real-time applications in the embedded systems due to their high performance, exceptional quality-of-service (QoS) and energy efficiency over superscalar uniprocessor architectures. Energy saving is important in the embedded system because it reduces the operating cost while prolongs lifetime and improves the reliability of the system. In this paper, contention-aware energy efficient static mapping using NoC-based heterogeneous MPSoC for real-time tasks with an individual deadline and precedence constraints is investigated. Unlike other schemes task ordering, mapping, and voltage assignment are performed in an integrated manner to minimize the processing energy while explicitly reduce contention between the communications and communication energy. Furthermore, both dynamic voltage and frequency scaling and dynamic power management are used for energy consumption optimization. The developed contention-aware integrated task mapping and voltage assignment (CITM-VA) static energy management scheme performs tasks ordering using earliest latest finish time first (ELFTF) strategy that assigns priorities to the tasks having shorter latest finish time (LFT) over the tasks with longer LFT. It remaps every task to a processor and/or discrete voltage level that reduces processing energy consumption. Similarly, the communication energy is minimized by assigning discrete voltage levels to the NoC links. Further, total energy efficiency is achieved by putting the processor into a low-power state when feasible. Moreover, this approach resolves the contention between communications that traverse the same link by allocating links to communications with higher priority. The results obtained through extensive simulations of real-world benchmarks demonstrate that CITM-VA approach outperforms state-of-the-art technique and achieves an average ~30% total energy improvement. Additionally, it maintains high QoS and robustness for real-time applications.

Highlights

  • Energy dissipation over the past decade in System-on-Chips (SoCs) has become a captious design constraint as it limits the performance, reliability and battery life [1]

  • NoC based heterogeneous Multiprocessor System-on-Chips (MPSoCs) architecture with Dynamic Voltage and Frequency Scaling (DVFS)-enabled processors is considered while contention and energy-aware static mapping for real-time Directed Acyclic Graph (DAG) tasks with individual deadlines and precedence constraints is studied

  • The energy performance of contention-aware integrated task mapping and voltage assignment (CITM-VA) scheme is evaluated by comparing it to a Genetic Algorithm (GA) based Energy-efficient Contentionaware Mapping (ECM) approach developed by Li and Wu [24]

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Summary

INTRODUCTION

Energy dissipation over the past decade in System-on-Chips (SoCs) has become a captious design constraint as it limits the performance, reliability and battery life [1]. H. Ali et al.: Contention & Energy-Aware Real-Time Task Mapping on NoC-Based Heterogeneous MPSoCs. A dramatic increase in their use is expected in the upcoming years and there will be hundreds of processors on a single chip [5]. NoC based heterogeneous MPSoC architecture with DVFS-enabled processors is considered while contention and energy-aware static mapping for real-time Directed Acyclic Graph (DAG) tasks with individual deadlines and precedence constraints is studied. Our Contention-aware Integrated Task Mapping and Voltage Assignment (CITM-VA) scheme guides the tasks and communications mapping to a more energy efficient solution Both DVFS and DPM are integrated to reduce the total energy consumption.

RELATED WORK
COMMUNICATION INTERCONNECT MODEL
ENERGY MODEL
RESULTS AND DISCUSSION
CONCLUSION
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