Abstract
Specification and evaluation are significant steps in developing computer systems. In the last decade essential CAD methods and tools have been evolved supporting design automation of VLSI chips and dedicated electronic systems. Nowadays software engineering, compiler design and scheduling techniques seem to be sufficiently understood to be fit together with hardware design technologies. This paper presents a CAD methodology to specify parallel computer architectures using a stripped-off hardware description language. Based on a compact hardware specification a corresponding compiler and simulator are generated to evaluate the architecture specified. Using these architecture specific compilers and simulators the modelled hard- and software system can be evaluated indicating optimization potential. Both compilers and simulators are generated making use of a central libraryof CPUs, busses and memory models.
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