Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing

Abstract

In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.