Abstract
Ovonic memory switching (OMS) and ovonic threshold switching (OTS) are the most attractive characteristics of the chalcogenides, where the former implements nonvolatile data storage in phase change materials (PCM) and the latter enables the high-density 3D integration of PCM. Wide-range temperature variation during device fabrication and electrical operation brings risks of stress and diffusion induced device failure, that urges the improvement of reliability in OTS and OMS devices. In this work, carbon layers with different thickness have been inserted between Ge2Sb2Te5 chalcogenide and TiN electrode, to improve the interface reliability. Carbon layer with optimized thickness can reduce the elements diffusion and lower the peeling risk at the interface. While, excessively thick carbon layers will cause Ge precipitation from the chalcogenide layer, leading to a fragile interface. Moreover, a low power consumption has been achieved in PCM cells with carbon layers, attributed to the blocked heat dissipation at the amorphous carbon layer and the consequential high-power efficiency. The application of carbon layer not only ensures the good reliability in OTS selectors and PCM devices, but also improves the power efficiency.
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