Abstract

The cornerstone of dynamic partial order reduction (DPOR) is the notion of independence that is used to decide whether each pair of concurrent events p and t are in a race and thus both $$p \cdot t$$ and $$t \cdot p$$ must be explored. We present constrained dynamic partial order reduction (CDPOR), an extension of the DPOR framework which is able to avoid redundant explorations based on the notion of conditional independence—the execution of p and t commutes only when certain independence constraints (ICs) are satisfied. ICs can be declared by the programmer, but importantly, we present a novel SMT-based approach to automatically synthesize ICs in a static pre-analysis. A unique feature of our approach is that we have succeeded to exploit ICs within the state-of-the-art DPOR algorithm, achieving exponential reductions over existing implementations.

Highlights

  • Partial Order Reduction (POR) is based on the idea that two interleavings can be considered equivalent if one can be obtained from the other by swapping adjacent, non-conflicting independent execution steps

  • We present an SMT-based approach to automatically synthesize independence constraints (ICs) for atomic blocks, whose applicability goes beyond the DPOR context

  • We experimentally show the exponential gains achieved by constrained dynamic partial order reduction (CDPOR) on some typical concurrency benchmarks used in the DPOR literature before

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Summary

Introduction

Partial Order Reduction (POR) is based on the idea that two interleavings can be considered equivalent if one can be obtained from the other by swapping adjacent, non-conflicting independent execution steps. The DynamicPOR (DPOR) algorithm, introduced by Godefroid [9] in 2005, was a breakthrough in the area because it does not need to look at the future It keeps track of the independence races witnessed along its execution and uses them to decide the required exploration dynamically, without the need of static approximation. CSDPOR does not use ICs (it rather checks state equivalence dynamically during the exploration) and exploits conditional (context-sensitive) independence only partially to extend the sleep sets. Our challenge is twofold: (i) extend the DPOR framework to exploit ICs during the exploration in order to both reduce the backtrack sets and expand the sleep sets as much as possible, (ii) statically synthesize ICs in an automatic pre-analysis. We experimentally show the exponential gains achieved by CDPOR on some typical concurrency benchmarks used in the DPOR literature before

Background
Basics of Partial Order Reduction
State-of-the-Art DPOR with Unconditional Independence
DPOR with Conditional Independence
Using Precomputed ICs Directly
Transitive Uniformity
The Constrained DPOR Algorithm
Automatic Generation of ICs Using SMT
The Basic Inference
IC for Blocks with Process Creation
Other Extensions
Experiments
Related Work and Conclusions
Full Text
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