Considerations for design of a complex multiplier

Abstract

The design of a multiplier for the multiplication of complex numbers is considered. The numbers are represented by two 13-b parts with the same 6-b exponent. Multiplication of complex numbers was examined from the perspectives of performance, complexity and silicon area. The design shares the Booth encoding for the real and imaginary parts, with only one Wallace tree of 4:2 adders for each part. The number of adders used in the multiplier is also reduced. VLSI CMOS technology and the relevant characteristics as they affect the implementation and performance are considered. The circuit has been designed and laid out using a 1.5- mu m standard CMOS process. >