Abstract
The performance of ΣΔ modulators (ΣΔMs) is highly dependent of that of their embedded switched-capacitor (SC) network. Therefore, detailed transient models of SC integrators become necessary when modeling ΣΔMs. This work presents a behavioral transient model of a SC integrator that includes the effects of the amplifier transconductance and output conductance relation; and the dynamic capacitive loading effect on the settling time. Unlike traditional behavioral models where this level of detail is usually omitted, the proposed model provides a convenient tool to aid in the design of low-power high-speed SC ΣΔMs. Additional nonidealities such as jitter, thermal noise and DAC mismatch are included in a dual-band GSM/WCDMA second-order multi-bit with individual level averaging (ILA) ΣΔM VHDL-AMS model. Experimental data is used to validate the model where it exhibits less than 3.0% of error in the signal-to-noise plus distortion ratio (SNDR).
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