Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

E Romero-Aguirre,Roberto Carrasco-Alvarez,A G Orozco-Lugo,R Parra-Michel

doi:10.1155/2012/236372

Abstract

In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115 MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards.

Highlights

IntroductionThere is need to develop communications systems capable of transmitting/receiving various types of information (data, voice, video, etc.) at high speed
There is need to develop communications systems capable of transmitting/receiving various types of information at high speed
We present a extended version of that paper, where a hardware-efficient architecture for configurable superimposed training (ST)/dependent superimpose training (DDST) transmitter that supports 4/16/64-QAM constellations is used to complement the results presented in [11], because all transmitted data—in each Monte Carlo trial—are generated by the proposed transmitter hardware instead of the transmitter simulation model programmed in Matlab

Summary

Introduction

There is need to develop communications systems capable of transmitting/receiving various types of information (data, voice, video, etc.) at high speed. Designing these systems is always an extremely difficult task, and, the system must be broken down into several stages each with a specific task. In order to deal with these problems, current communication standards specify the transmission of pilot signals which are known in the receiver, allowing an ease estimation of the communication channel. [a]k denotes the kth element of vector a. [a]m:n denotes a vector conformed with the elements of a as follows: [[a]m, [a]m+1, .

System Model

Systolic Channel Estimator Architecture

Results

Conclusions