Configurable sram macro design to resist total dose effects

Abstract

This paper presents a size-configurable architecture for embedded SRAMs in radiation-tolerant, 0.18-mum CMOS, ASIC designs. A digital library that includes the basic components for building the circuit is developed by systematically using enclosed-gate transistors and guard rings to reduce leakage currents. The physical layout data of the memory design includes a memory cell array and peripheral blocks: column address decoder, row address decoder, timing control logic, I/O circuitry and power lines. Some blocks are re-configurable to accommodate various word counts and bit capacities. In the design, some low-power techniques are adopted, such as address transition detection, divided word lines, and self-timing circuitry. A dynamic divided word line scheme, which combines a divided word line structure and an automatic power down (APD) scheme, is used for the architecture. A test chip of a SRAM macro has been designed, simulated and fabricated to verify the proposed architecture. The simulation results indicate that the developed memory functions as supposed