Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism

Abstract

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern SoCs. Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for two-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel 4-transistor gain-cell, which provides up-to two independent read and write ports (2R2W), with a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, offering up-to 3 × reduction in bitcell area compared to other dual-ported SRAM memory options, and 100% memory availability, as opposed to conventional dynamic memories.