Confidence Based Power Aware Testing

Abstract

In modern deep sub-micron technology, it is very crucial to have quality product with low power test and desired level of fault coverage. In this paper, we address a technique to reduce test length with efficiently managed scan power and higher test quality, targeting to achieve a desired level of fault coverage with all essential (marked) faults being covered as well. This can aid in achieving a trade-off between test time and quality assurance of the product. It can provide a level of confidence about the correctness of system functionalities for the amount of test effort incorporated. Experimental results of our approach on ISCAS'89 benchmark circuits show a good reduction in test length with improved fault coverage. It also makes the resulting test set power aware.