Cone extraction technique for incremental static timing analysis

Abstract

As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes. Engineering Change Order (ECO), Static Timing Analysis (STA), Incremental Static Timing Analysis, VLSI design