Abstract
Several limitations of the polysilicon gate in VLSI have led to the development of a silicide/polysilicon material as all alternative to polysilicon. Recently, rapid thermal processing has been investigated for annealing such polycide films. We report here the electrical-conductivity changes during the process of rapid thermal annealing in CVD tungsten silicide films. It is shown that electrical resistivity initially increases due to changes in the silicon to tungsten ratio and then drops to about one-tenth of the initial value, thus suggesting a minimum time and power required for achieving low-resistivity tungsten silicide films in VLSI interconnections.
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