Conductive-paste-based high-yielding interconnection process for c-Si photovoltaic modules with 50 µm thin cells

Abstract

Thin crystalline silicon (c-Si) photovoltaic (PV) cells (< 100 µm) have the potential to curtail manufacturing costs by reducing the amount of Si needed per wafer. However, thermo-mechanical stress induced by high-temperature (> 200 °C) soldering causes frequent wafer breakage in thin c-Si-based modules. Hence, in this work, we proposed low-temperature interconnection method using conductive paste (CP) for thin c-Si PV modules and systematically studied the modules’ electrical and mechanical properties as a function of annealing temperature of CP. The potential advantage of this method is significantly reduced wafer bowing due to the low-temperature tabbing (< 150 °C) of CP dispensed cells to ribbons using heat and pressure during lamination. Module degradation and peel stress tests indicated that CP cured above its melting point provides stable (degraded 3.0% after 500 h damp heat test) and efficient current flow paths. By contrast, CP annealed below the melting point is vulnerable to thermal and humidity stress, leading to 7.8% degraded output after the test. Given these features, stable, large modules with thin c-Si cells integrated using a CP approach (laminated at 150 °C) were successfully realized without cell breakage.