Conduction Mechanisms at SiO<sub>2</sub>/4H-SiC Interfaces in MOS-Based Devices Subjected to Post Deposition Annealing in N<sub>2</sub>O

Abstract

This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.