Concurrent generation of pseudo random numbers with LFSR of Galois type

Abstract

In this paper we consider the implementation of parallel test patterns generation which is used as a basic building block in built-in-self test (BIST) design. The proposed design can drive several circuits under test (CUT) within a complex VLSI IC. For parallel test pattern generation a LFSR of Galois type is used. Mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented a LFSR that generates two PRNs in parallel. The achieved speed up is between 1.33 and 2, and depends on the characteristics of used primitive polynomial.