Abstract

Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which a processor resource may serve an incoming request, when its access is arbitrated using time-predictable policies such as round-robin or FIFO. We call this value upper-bound delay ( $ubd$ ). Deriving trustworthy $ubd$ statically is possible when sufficient public information exists on the timing latency incurred on access to the resource of interest. Unfortunately however, that is rarely granted for commercial-of-the-shelf (COTS) processors. Therefore, the users resort to measurement observations on the target processor and thus compute a “measured” $ubd_{m}$ . However, using $ubd_{m}$ to compute worst-case execution time values for programs running on COTS multicore processors requires qualification on the soundness of the result. In this paper, we present a measurement-based methodology to derive a $ubd_m$ under round-robin (RoRo) and first-in-first-out (FIFO) arbitration, which accurately approximates $ubd$ from above, without needing latency information from the hardware provider. Experimental results, obtained on multiple processor configurations, demonstrate the robustness of the proposed methodology.

Highlights

  • IntroductionThe real-time systems industry has started to consider multicore processors (multicores in the following) as their baseline computing platform, in response to the increasing performance requirement of new applications

  • The real-time systems industry has started to consider multicore processors as their baseline computing platform, in response to the increasing performance requirement of new applications

  • 3) We demonstrate our methodology to derive trustworthy ubdm for the bus and memory controller on a multicore setup that matches that of the Cobham Gaisler NGMP processor [8], a 4-core multicore considered by the European Space Agency for future missions, which embeds per-core data and instruction caches connected to the L2 with an Advanced Microcontroller Bus Architecture (AMBA) AHB bus

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Summary

Introduction

The real-time systems industry has started to consider multicore processors (multicores in the following) as their baseline computing platform, in response to the increasing performance requirement of new applications. This situation extends across a variety of application domains, including automotive [34], avionics [32], and space [33]. In spite of the potential benefit to available performance, embracing multicores for the real-time systems industry is a difficult challenge. Mainstream COTS multicores are designed to improve average performance rather than time predictability, which is an essential ingredient to compute tight and sound worst-case execution time (WCET) bounds for real-time software programs. At the present state of the art, analysis solutions capable of delivering tight and sound WCET bounds for COTS multicores do not yet exist, and execution-time bounds (ETB) are derived instead, which may or may not be true upperbounds

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