Computer architecture for die stacking

Abstract

Three-dimensional die-stacking technologies are rapidly maturing, with intense research and development happening in the areas of manufacturing, EDA/CAD, test, and yield improvement. When die-stacking technology has reached the point of economic viability for high-volume manufacturing, chip and system designers must have complete architectures ready to take advantage of this exciting new technology. Computer architecture researchers are showing great interest in 3D technology. This paper summarizes some of the major directions that academic researchers are currently exploring, highlights some of these efforts, and discusses future opportunities in these and other areas of computer and system architectures. In particular, this paper covers 3D opportunities for compute (including processor- and application-specific accelerators), memory, and the integration of other technologies from a computer architecture perspective. This paper also explores how collaboration between computer architecture and other fields may provide further value for the entire die-stacking ecosystem.