Abstract
An algebraic expression for the Preisach hysteron, which is a non-ideal (delayed) relay operator, is formulated for a computationally efficient real-time implementation. This allows representing the classical scalar Preisach hysteresis model as a summation of a large number of weighted hysterons which computation can be accomplished in parallel. The latter makes possible an efficient FPGA or ASIC realization of the scalar Preisach hysteresis model that can be useful for multiple applications. The signal flow which specifies the model implementation is provided in form of the block diagram. The proposed computation of Preisach hysterons, aggregated to the entire Preisach hysteresis model, is evaluated numerically and on a real-time hardware platform.
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