Abstract
The graphene nanoribbon (GNR) tunneling field effect transistor (TFET) has been a promising candidate for a future low power logic device due to its sub-60 mV/dec subthreshold characteristic and its superior gate control on the channel electrons due to its one-dimensional nature. Even though many theoretical studies have been carried out, it is not clear that GNR TFETs would outperform conventional silicon metal oxide semiconductor field effect transistors (MOSFETs). With rigorous atomistic simulations using the p/d orbital tight-binding model, this study focuses on the optimization of GNR TFETs by tuning the doping density and the size of GNRs. It is found that the optimized GNR TFET can operate at a half of the supply voltage of silicon nanowire MOSFETs in the ballistic limit. However, a study on the effects of edge roughness on the performance of the optimized GNR TFET structure reveals that experimentally feasible edge roughness can deteriorates the on-current performance if the off-current is normalized with the low power requirement specified in the international technology roadmap for semiconductors.
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